The disclosure relates to the field of computer systems, and, more particularly, to a computer system for improving circuit designs.
During the very-large-scale integration (“VLSI”) design flows, physical synthesis tools (in particular, placement, timing optimization, routing and/or the like) may be invoked iteratively while circuit designers make changes to floorplans, timing assertions, logic implementations, etc. The synthesis result may be back annotated for decision making of further design changes.